Sunday, April 24, 2011

MICROPROCESSOR LAB PROGRAMS - 1

MICROPROCESSOR


32-bit SUBTRACTION-DIRECT ADDRESSING:


stc
cmc
lxi h,1122
lxi d,3344
mvi b,00
lda 8050
sub l
sta 8060
lda 8051
sbb h
sta 8061
lda 8052
sbb e
sta 8062
lda 8053
sbb d
sta 8063
jnc l
inr b
mov a,b
sta 8064
l:
hlt

COUNT DOWN 0-9-0


ADDRESS 8000
L:         LXI H,8070
L1:        MVI D,0A
MVI A,90
OUT 31
MOV A,M
OUT 30
CALL 9000
INX H
DCR D
JNZ L1
MVI D,0A
MVI A,90
L2:        DCX H
            OUT 31
            MOV A,M
            OUT 30
            CALL 9000
            DCR D
            JNZ L2
            CALL 9000
            JMP L

ADDRESS 8070      (7-Segment Display coding)
8070 – F3
8071 – 60
8072 – B5
8073 – F4
8074 – 66
8075 – D6
8076 – D7
8077 – 70
8078 – F7
8079 – F6

ADDRESS 9000       (Delay program of 0.5sec)
L:         LXI B,FFFF
            DCX B
            MOV A,C
            ORA B
            JNZ L
            RET


DISPLAYING THE TRUTH TABLE OF HALF ADDER AND SUBTRACTOR:



L
  LXI H,8070
MVI D,04
L1
MVI A,90
OUT 31
MOV A,M
OUT 30
MVI A,92
OUT 31
INX H
MOV A,M
OUT 30
MVI A,94
OUT 31
INX H
MOV A,M
OUT 30
MVI A,95
OUT 31
INX H
MOV A,M
OUT 30
MOV E,A
CALL DELAY
MOV A,E
INX H
DCR D
JNZ L1
JMP L
HLT

FINDING A PRIME NUMBER:

MVI A,XàNumber to be given.
MVI B,02
L1: MVI A,X
SUB B
JM L
JZ L5
L2:JZ L4
SUB B
JM L5
JMP L2
L5:INR B
JMP L1
L4:INR C
JMP L5
L:MVI A,00
SUB C
JM L6
JP L7
L6:MVI A,93
OUT 31
MVI A,76
OUT 30
L7:MVI A,94
OUT 31
MVI A,47
OUT 30
HLT

AND, OR,  NOT GATES :

L :LXI H,8070
    MVI D,04
L1:MVI A,90
      OUT 31
      MOV A,M
      OUT 30
       MVI A,92
       OUT 31
       INX H
       MOV A,M
       OUT 30
       MVI A,94
       OUT 31
       INX H
       MOV A,M
       OUT 30
       MOV E,A
       CALL 9000
       MOV A,E
       INX H
       DCR D
       JNZ L1
       JMP L
DELAY PROGRAM:
        LXI B,FFFF
   L2:DCX B
        MOV A,C
        ORA B
        JNZ L2
        RET
BEFORE EXECUTION
AND:
8070-66             8076-F3                  
8071-66             8077-66
8072-66             8078-66
8073-66             8079-F3
8074-F3             807A-F3
8075-66             807B-F3
     OR:
807C-66             8082-F3                  
807D-66             8083-66
807E-66             8084-F3
807F-66             8085-F3
8080-F3             8086-F3
8081-F3             8087-F3

NOT:
8088-66           
8089-F3
808A-F3
808B-66

D FLIP FLOP:


lxi h,9000
mov a,m
inx h
mov b,m
cpi 01
jnz l
inx h
mov m,a
l:
inx h
mov m,b
hlt

T  FLIP FLOP:


lxi h,9000
mov a,m
inx h
mov b,m
cpi 01
jnz l
inx h
mov m,a
l:
mov a,b
mov e,a
cma
inx h
ana m
mov c,a
mov a,m
cma
mov d,a
ana d
ora c
mov m,a
hlt

FULL ADDER:


lxi h,9000
mov a,m
inx h
mov b,m
inx h
mov c,m
add b
adc c
mov b,a
ani 01
sta 8050
mov a,b
rrc
ani 01
sta 8051
hlt

           

To compute y = ((x*x)-2x+2)/2



LXI H,8050h
MVI A,00h
MVI E,02h
MOV B,M
MOV C,M
L: ADD C
DCR B
JNZ L
MOV B,A
MVI A,00h
L1: ADD C
DCR E
JNZ L1
MOV E,A
MOV A,B
SUB E
ADI 02
MOV D,A
MVI A,00
SUB A
MOV A,D
RAR
STA 9050
HLT

To compute 1+2+3+…+n and simultaneously store in memory address from 1 to n and then the sum:


LXI H,8050h
LXI D,9000h
LDAX D
MOV B,A
MVI A,00
MVI C,01
L  MOV M,C
ADD C
INR C
DCR B
INX H
JNZ L
MOV M,A
HLT

Hex to octal:


LXI H,9000     
MOV A,M
l:         
SUI 08            
INR
JNC  L
ADI 08            
DCR B           
INX
MOV M,A       
MOV A,B       
MVI B,00                    
CPI 08            
JNC L                         
STA 9003      
HLT    

BEFORE EXECUTION                                                              AFTER EXECUTION
9000-FF                                                                                     9000 –FF   (hexadecimal data )
9001-00                                                                                    9001-07
9002-00                                                                                    9002-07
9003-00                                                                                    9003-03
The octal equivalent number of hexadecimal data FF is 377 and is stored in address 9003, 9002, 9001 respectively. Thus hexadecimal number to octal number using 8085 microprocessor kit is done successfully.

 

MULTIPLEXING:


lxi h,9000
mov a,m
sui 00
jnz p
inx h
mov a,m
sta 8050
jmp l3
p:
sui 01
jnz l1
lxi h,9002
mov a,m
sta 8050
jmp l3
l1:
sui 01
jnz l2
lxi h,9003
mov a,m
sta 8050
jmp l3
l2:
lxi h,9004
mov a,m
sta 8050
l3:
hlt

32 BIT DIVISION:


lxi d,0000
mvi b,02h
lhld 9000
l1:
mov a,l
l:
inx d
sub b
jnc l
mov l,a
dcr h
mov a,h
cpi ff
jnz l1
shld 9000
lhld 9003
dcr l
mov a,l
cpi ff
jnz l1
dcr h
mov a,h
cpi ff
shld 9003
jnz l1
inr h
inr l
shld 9003
lhld 9000
inr h
mov a,l
add b
mov l,a
shld 9000
dcx d
xchg
shld 9100
hlt


To write a program to manipulate and display the value of given mathematical expression as well as to display the value of individual elements containing the variables:

The given expression is:     


PROGRAM

MVI D, VALUE OF X
MOV C, D
MVI A, 00                     [VALUE OF IS COMPUTED]
ADD D (L1)
DCR C
JNZ L1
STA 9000

MVI A, 00
MVI E, 02
ADD D (L2)                    [VALUE OF IS COMPUTED]
DCR E
JNZ L2
STA 9001

MVI A, 00
MVI E, 05
ADD D (L3)                    [VALUE OF IS COMPUTED]
DCR E
JNZ L3
STA 9002

LXI H, 9000
MOV A, M
INX H
SUB M
ADI 04
INX H
MVI B, 00                         [THE VALUE OF OVERALL EXPRESSION IS COMPUTED]
SUB M (L4)
INR B
JNC L4
DCR B
INX H
MOV A, B
MOV M, A

LXIH, 9000
MOV A, M
MVI B, 10
MVI C, 00
SUB B (L5)
INR C
JNC L5
DCR C
ADD B                  [SEPARATE THE UNITS AND TENS DIGITS OF AND DISPLAY THEM]
STA 9004
MOV A, C
STA 9005
MVI A, 90
OUT 31
LXI H, 9005
MOV A, M
OUT 30
MVI A, 91
OUT 31
LXI H, 9004
MOV A, M
OUT 30
CALL 9050              [CALL DELAY]

LXIH, 9001
MOV A, M
MVI B, 10
MVI C, 00
SUB B (L6)
INR C
JNC L6
DCR C
ADD B                  [SEPARATE THE UNITS AND TENS DIGITS OF AND DISPLAY THEM]
STA 9006
MOV A, C
STA 9007
MVI A, 90
OUT 31
LXI H, 9007
MOV A, M
OUT 30
MVI A, 91
OUT 31
LXI H, 9006
MOV A, M
OUT 30
CALL 9050              [CALL DELAY]

LXIH, 9002
MOV A, M
MVI B, 10
MVI C, 00
SUB B (L7)
INR C
JNC L7
DCR C
ADD B                  [SEPARATE THE UNITS AND TENS DIGITS OF 5 AND DISPLAY THEM]
STA 9008
MOV A, C
STA 9009
MVI A, 90
OUT 31
LXI H, 9009
MOV A, M
OUT 30
MVI A, 91
OUT 31
LXI H, 9008
MOV A, M
OUT 30
CALL 9050              [CALL DELAY]

LXI H, 9003
MOV A, M
MVI B, 10
MVI C, 00
SUB B (L8)
INR C
JNC L8
DCR C
ADD B
STA 900A
MOV A, C        [SEPARATE THE UNITS AND TENS DIGITS OF THE VALUE OF EXPRESSION AND DISPLAY]
STA 900B
MVI A, 90
OUT 31
LXI H, 900B
MOV A, M
OUT 30
MVI A, 91
OUT 31
LXI H, 900A
MOV A, M
OUT 30

DELAY PROGRAM:

9050:
 MVI C, 00
LXI B, FFFF
DCX B
MOV A, C
ORA B
JNZ L
RET

RESULT:

FOR X=4

9000 CONTAINS 16( )
9001 CONTAINS 8( )
9002 CONTAINS 20( )
90003 CONTAINS THE VALUE OF EXPRESSION 0

  
DECODER (3 TO 8):

AIM:

To decode the given 3 bit value.
ALGORITHM:
1)    Use 3 registers (E,B,C) to store the 3 input values.
2)    The output is 8 bit value and each bit is stored in the address from 9000 to 9007(D0-D7).
3)    Use the formulas mentioned below,
        _  _  _                                                         _  _ 
D0= E  B C                                                 D1= E  B C
        _      _                                                         _  
D2= E  B C                                                 D3= E  B C
            _  _                                                             _  
D4= E  B C                                                 D5= E  B C
                _
D6= E  B C                                                 D7= E B C
4)    The command CMA is used to compliment the register.
5)    AND operation is performed between the registers by the command ANA.
6)    Accumulator is used to store the register values temporarily and also for AND operation.
RESULT:
The given 3 bit value is decoded to 8 bit.


ADDRESS
HEXCODE
LABEL
MNEMONICS
8000
1E

MVI E,00
8001
00


8002
06

MVI B,00
8003
00


8004
0E

MVI C,00
8005
00


8006
21

LXI H,9000
8007
00


8008
90


8009
7B

MOV A,E
800A
2F

CMA
800B
5F

MOV E,A
800C
78

MOV A,B
800D
2F

CMA
800E
47

MOV B,A
800F
79

MOV A,C
8010
2F

CMA
8011
4F

MOV C,A
8012
CD

CALL 8050
8013
50


8014
80


8015
79

MOV A,C
8016
2F

CMA
8017
4F

MOV C,A
8018
CD

CALL 8050
8019
50


801A
80


801B
78

MOV A,B
801C
2F

CMA
801D
47

MOV B,A
801E
79

MOV A,C
801F
2F

CMA
8020
4F

MOV C,A
8021
CD

CALL 8050
8022
50


8023
80


8024
79

MOV A,C
8025
2F

CMA
8026
4F

MOV C,A
8027
CD

CALL 8050
8028
50


8029
80


802A
7B

MOV A,E
802B
2F

CMA
802C
5F

MOV E,A
802D
78

MOV A,B
802E
2F

CMA
802F
47

MOV B,A
8030
79

MOV A,C
8031
2F

CMA
8032
4F

MOV C,A
8033
CD

CALL 8050
8034
50


8035
80


8036
79

MOV A,C
8037
2F

CMA
8038
4F

MOV C,A
8039
CD

CALL 8050
803A
50


803B
80


803C
79

MOV A,C
803D
2F

CMA
803E
4F

MOV C,A
803F
78

MOV A,B
8040
2F

CMA
8041
47

MOV B,A
8042
CD

CALL 8050
8043
50


8044
80


8045
79

MOV A,C
8046
2F

CMA
8047
4F

MOV C,A
8048
CD

CALL 8050
8049
50


804A
80


804B
76

HLT
8050
79

MOV A,C
8051
A0

ANA B
8052
A3

ANA E
8053
E6

ANI 01
8054
01


8055
77

MOV M,A
8056
23

INX H
8057
C9

RET

PARITY CHECK




Mvi b,00



Mvi a,05



Mov c,a
L1
Rlc

Jnc l





Inr b
L
Cmp c

Jnz l1





Mov a,b
L2
Sui 02



Jnc l2





Adi 02



Jnz l3





Mvi a,90



Out 31



Mvi a,97



Out 30



Mvi a,91



Out 31



Mvi a,e3



Out 30



Mvi a,92



Out 31



Mvi a 97



Out 30



Mvi a,73



Out 30



Jmp l4




L3
Mvi a,90



Out 31



Mvi a, f3



Out 30



Mvi a,91



Out 31



Mvi a,e5



Out 30



Mvi a,92



Out 31



Mvi a,e5



Out 30


L4
Hlt


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